This relates to integrated circuits such as integrated circuits with memory, and more particularly, to circuitry for detecting soft memory errors in integrated circuits such as programmable integrated circuits.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data. The configuration data is loaded into memory elements to configure the devices to perform the functions of the custom logic circuit.
Memory elements are often based on random-access-memory (RAM) cells. Because the RAM cells are loaded with configuration data during device programming, the RAM cells are sometimes referred to as configuration memory or configuration random-access-memory cells (CRAM).
During normal operation of a programmable device, loaded CRAM cells produce static output signals that are applied to the gates of transistors (e.g., pass transistors). The CRAM output signals turn some transistors on and turn other transistors off. This selective activation of certain transistors on the device customizes the operation of the device so that the device performs its intended function.
When operating in a system, programmable devices are subject to environmental background radiation. Particularly in modern programmable devices that contain large numbers of CRAM cells, there is a possibility that a radiation strike on a CRAM cell will cause the CRAM cell to change its state. For example, a CRAM cell storing a “one” configuration bit may flip its state so that the cell erroneously stores a “zero” bit. When a CRAM cell changes state, the transistor being controlled by that CRAM cell will be placed into an erroneous state. The transistor might, for example, be turned on when it should have been turned off.
Radiation-induced errors that arise in configuration random-access-memory cells are sometimes referred to as soft errors. One way in which soft errors can be addressed is to change the design of the configuration random-access-memory cells. However, changes to the configuration random-access-memory cells can introduce undesired circuit complexity and can consume additional circuit real estate. As a result, it is often necessary to use a configuration random-access-memory cell architecture that occasionally produces soft errors.
Programmable devices sometimes include error detection circuitry that continuously monitors an entire array of CRAM cells. If an error is detected in the array, an error flag may be set. Systems that require highly reliable operations can monitor the status of the error flag to determine whether the programmable device has experienced any soft errors. So long as no errors are present, the system allows the programmable device to operate normally. If, however, the state of the error flag indicates that one of the configuration random-access-memory cells on the device has exhibited a soft error, the system can reconfigure the device by reloading the original configuration data into the configuration random-access-memory cells.
Conventional error detection circuitry includes a data register and a linear feedback shift register. A given frame (i.e., a column of memory elements that are connected to a shared address line) is read and latched by the data register. The data register then shifts the given frame into the linear feedback shift register.
Each frame in the programmable device is read and shifted into the linear feedback shift register. The linear feedback shift register provides output values that are compared to preloaded cyclic redundancy check (CRC) values. If the values match, then the memory cells in that particular frame (if error detection is performed on a per-frame basis) or device (if error detection is performed on a per-chip basis) are error free. If the values do not match, then at least one soft error exists in that particular frame or device.
Detecting soft errors using this approach is slow, because scan time is linearly dependent on the number of memory elements being scanned. Shifting latched data into the linear feedback shift register requires numerous clock cycles and consumes large amount of dynamic power. As design complexity and the number of memory cells increase in future generations of integrated circuits, detecting soft errors using this type of error detection circuitry may be unacceptably slow and may consume significant amounts of power.
It would therefore be desirable to be able to provide integrated circuits with improved error detection circuitry.